PIC instruction listings
The PIC instruction set refers to the set of instructions that a Microchip Technology PIC or dsPIC microcontroller supports. The instructions are usually programmed into the Flash memory of the processor, and automatically executed by the microcontroller on startup.
PICmicro chips have a Harvard architecture, and instruction words are unusual sizes. Originally, 12-bit instructions included 5 address bits to specify the memory operand, and 9-bit branch destinations. Later revisions added opcode bits, allowing additional address bits.
In the instruction set tables that follow, register numbers are referred to as "f", while constants are referred to as "k". Bit numbers (0–7) are selected by "b". The "d" bit selects the destination: 0 indicates W, while 1 indicates that the result is written back to source register f. The C and Z status flags may be set based on the result; otherwise they are unmodified. Add and subtract (but not rotate) instructions that set C also set the DC (digit carry) flag, the carry from bit 3 to bit 4, which is useful for BCD arithmetic.
Architecture
Memory operands are also referred to as "registers". Most are simply general-purpose storage (RAM), while some locations are reserved for special function registers. Except for a single accumulator (called W), almost all other registers are memory-mapped, even registers like the program counter and ALU status register. (The other exceptions, which are not memory-mapped, are the return address stack, and the tri-state registers used to configure the GPIO pins.)
The instruction set does not contain conditional branch instructions. Instead, it contains conditional skip instructions which cause the following instruction to be ignored. A conditional skip followed by an unconditional branch performs a conditional branch. The skip instructions test any bit of any register. The ALU status register is one possibility.
Memory operands are specified by absolute address; the location is fixed at compile time. To provide indirect addressing, a pair of special function registers are provided:
- The file select register (
FSR) is written with the address of the desired memory operand, after which - The indirect file register (
INDF) becomes an alias for the operand pointed to by the FSR.
This mechanism also allows up to 256 bytes of memory to be addressed, even when the instruction set only allows 5- or 7-bit memory operands. Models with more registers (special function registers plus RAM) than fit into the instruction provide multiple banks of memory, and use one of two mechanisms for accessing them:
- Most baseline core devices, and some mid-range core devices, use the high-order bits of the file select register to select the current register bank.
- More recent models have a separate bank select register, and a
MOVLBinstruction to set it.
PIC processors with more than 256 words of program use paged memory. The internal program counter and return stack are as wide as necessary to address all memory, but only the low 8 bits are visible to software in the PCL ("PC low") register. There is an additional PCLATH ("PC latch high") register which is only modified by software. Any operation which does not specify the full destination address (such as a 9-bit GOTO or an 8-bit write to the PC register) fills in the additional high bits from the corresponding part of PCLATH. (Some PIC18 processors extend this beyond 16 bits with a PCLATU register to supply bits 16–23.)
Baseline core devices (12 bit)
| 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | Description |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | opcode | Miscellaneous instructions | |||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP | No operation (MOVW 0,W) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | OPTION | Copy W to OPTION register | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | SLEEP | Go into standby mode | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLRWDT | Restart watchdog timer | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | f | TRIS f | Copy W to tri-state register (f = 1, 2 or 3) | |||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | k | MOVLB k* | Set bank select register to k | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | RETURN† | Return from subroutine, W unmodified | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | RETFIE† | Return from interrupt; return & enable interrupts | ||
| 0 | 0 | opcode | d | register | ALU operations: dest ← OP(f,W) | ||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | f | MOVWF f | dest ← W | ||||||
| 0 | 0 | 0 | 0 | 0 | 1 | d | f | CLR f,d | Z | dest ← 0, usually written CLRW or CLRF f | |||||
| 0 | 0 | 0 | 0 | 1 | 0 | d | f | SUBWF f,d | C | Z | dest ← f−W (dest ← f+~W+1) | ||||
| 0 | 0 | 0 | 0 | 1 | 1 | d | f | DECF f,d | Z | dest ← f−1 | |||||
| 0 | 0 | 0 | 1 | 0 | 0 | d | f | IORWF f,d | Z | dest ← f | W, logical inclusive or | |||||
| 0 | 0 | 0 | 1 | 0 | 1 | d | f | ANDWF f,d | Z | dest ← f & W, logical and | |||||
| 0 | 0 | 0 | 1 | 1 | 0 | d | f | XORWF f,d | Z | dest ← f ^ W, logical exclusive or | |||||
| 0 | 0 | 0 | 1 | 1 | 1 | d | f | ADDWF f,d | C | Z | dest ← f+W | ||||
| 0 | 0 | 1 | 0 | 0 | 0 | d | f | MOVF f,d | Z | dest ← f | |||||
| 0 | 0 | 1 | 0 | 0 | 1 | d | f | COMF f,d | Z | dest ← ~f, bitwise complement | |||||
| 0 | 0 | 1 | 0 | 1 | 0 | d | f | INCF f,d | Z | dest ← f+1 | |||||
| 0 | 0 | 1 | 0 | 1 | 1 | d | f | DECFSZ f,d | dest ← f−1, then skip if zero | ||||||
| 0 | 0 | 1 | 1 | 0 | 0 | d | f | RRF f,d | C | dest ← CARRY<<7 | f>>1, rotate right through carry | |||||
| 0 | 0 | 1 | 1 | 0 | 1 | d | f | RLF f,d | C | dest ← F<<1 | CARRY, rotate left through carry | |||||
| 0 | 0 | 1 | 1 | 1 | 0 | d | f | SWAPF f,d | dest ← f<<4 | f>>4, swap nibbles | ||||||
| 0 | 0 | 1 | 1 | 1 | 1 | d | f | INCFSZ f,d | dest ← f+1, then skip if zero | ||||||
| 0 | 1 | opc | bit | register | Bit operations | ||||||||||
| 0 | 1 | 0 | 0 | bit | f | BCF f,b | Clear bit b of f | ||||||||
| 0 | 1 | 0 | 1 | bit | f | BSF f,b | Set bit b of f | ||||||||
| 0 | 1 | 1 | 0 | bit | f | BTFSC f,b | Skip if bit b of f is clear | ||||||||
| 0 | 1 | 1 | 1 | bit | f | BTFSS f,b | Skip if bit b of f is set | ||||||||
| 1 | 0 | opc | k | Control transfers | |||||||||||
| 1 | 0 | 0 | 0 | k | RETLW k | Set W ← k, then return from subroutine | |||||||||
| 1 | 0 | 0 | 1 | k | CALL k | Call subroutine, 8-bit address k | |||||||||
| 1 | 0 | 1 | k | GOTO k | Jump to 9-bit address k[1] | ||||||||||
| 1 | 1 | opc | 8-bit immediate | Operations with W and 8-bit literal: W ← OP(k,W) | |||||||||||
| 1 | 1 | 0 | 0 | k | MOVLW k | W ← k | |||||||||
| 1 | 1 | 0 | 1 | k | IORLW k | Z | W ← k | W, bitwise logical or | ||||||||
| 1 | 1 | 1 | 0 | k | ANDLW k | Z | W ← k & W, bitwise and | ||||||||
| 1 | 1 | 1 | 1 | k | XORLW k | Z | W ← k ^ W, bitwise exclusive or | ||||||||
| 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | Description |
*: Extended instruction, not available on most 12-bit PICs. Of the models with extended RAM, most (e.g. 16C5x, 16F5x) extend the register address space using the high-order bits of the FSR. A few (e.g. PIC12F529T39A) have a separate bank select register which can be set with this instruction.
†: Extended instruction, only available on "enhanced baseline" PICs. Only the very few models (16F527, 16F570, MCV20A) with interrupt support (and a 4-level stack) include these instructions. All such models also include MOVLB.
ELAN Microelectronics clones (13 bit)
ELAN Microelectronics Corp. make a series of PICmicro-like microcontrollers with a 13-bit instruction word.[2] The instructions are mostly compatible with the mid-range 14-bit instruction set, but limited to a 6-bit register address (16 special-purpose registers and 48 bytes of RAM) and a 10-bit (1024 word) program space.
The 10-bit program counter is accessible as R2. Reads access only the low bits, and writes clear the high bits. An exception is the TBL instruction, which modifies the low byte while preserving bits 8 and 9.
The 7 accumulator-immediate instructions are renumbered relative to the 14-bit PICmicro, to fit into 3 opcode bits rather than 4, but they are all there, as well as an additional software interrupt instruction.
There are a few additional miscellaneous instructions, and there are some changes to the terminology (the PICmicro OPTION register is called the CONTrol register; the PICmicro TRIS registers 1–3 are called I/O control registers 5–7), but the equivalents are obvious.
| 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | Description |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | opcode | Miscellaneous instructions | ||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP* | No operation (MOVW 0,W) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | DAA† | C | Decimal Adjust after Addition | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | CONTW* | Write CONT register (CONT ← W) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | SLEEP* | Go into standby mode (WDT ← 0, stop clock) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLRWDT* | Restart watchdog timer (WDT ← 0) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | f | IOW f* | Copy W to I/O control register (f = 5–7, 11–15) | |||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | ENI† | Enable interrupts | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | DISI† | Disable interrupts | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | RET | Return from subroutine, W unmodified | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | RETI | Return from interrupt; return & enable interrupts | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | CONTR† | Read CONT register (W ← CONT) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | f | IOR f† | Copy I/O control register to W (f = 5–7, 11–15) | |||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | TBL† | C | Z | PCL += W, preserve PC bits 8 & 9 |
| 0 | 0 | opcode | d | register | ALU operations same as 12- and 14-bit PIC | |||||||||||
| 0 | 1 | opc | bit | register | Bit operations same as 12- and 14-bit PIC | |||||||||||
| 1 | 0 | c | k | Control transfers same as 14-bit PIC | ||||||||||||
| 1 | 1 | opcode | 8-bit immediate | Operations with W and 8-bit literal: W ← OP(k,W) | ||||||||||||
| 1 | 1 | 0 | op | k | MOV/IOR/AND/XOR, same as 12-bit PIC | |||||||||||
| 1 | 1 | 1 | 0 | 0 | k | RETLW k | W ← k, then return from subroutine | |||||||||
| 1 | 1 | 1 | 0 | 1 | k | SUBLW k | C | Z | W ← k−W (W ← k+~W+1) | |||||||
| 1 | 1 | 1 | 1 | 0 | k | INT k† | Push PC, PC ← k (software interrupt, usually k=1) | |||||||||
| 1 | 1 | 1 | 1 | 1 | k | ADDLW k | C | Z | W ← k+W | |||||||
| 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | Description |
*: Same opcode as 12-bit PIC
†: Instruction unique to EM78 instruction set with no PIC equivalent
Some models support multiple ROM or RAM banks, in a manner similar to other PIC microcontrollers.
Mid-range core devices (14 bit)
These devices feature a 14-bit wide code memory, and an improved 8 level deep call stack. The instruction set differs very little from the baseline devices, but the 2 additional opcode bits allow 128 registers and 2048 words of code to be directly addressed. There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.
| 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | Description |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | opcode | Miscellaneous instructions | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP | No operation (MOVW 0,W) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | RETURN | Return from subroutine, W unmodified | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | RETFIE | Return from interrupt | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | OPTION | Copy W to OPTION register (deprecated) | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | SLEEP | Go into standby mode | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | CLRWDT | Restart watchdog timer | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | f | TRIS f | Copy W to tri-state register (f = 1, 2 or 3) (deprecated) | |||
| 0 | 0 | opcode | d | register | ALU operations: dest ← OP(f,W) | ||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | f | MOVWF f | f ← W | ||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | d | f | CLR f,d | Z | dest ← 0, usually written CLRW or CLRF f | |||||||
| 0 | 0 | 0 | 0 | 1 | 0 | d | f | SUBWF f,d | C | Z | dest ← f−W (dest ← f+~W+1) | ||||||
| 0 | 0 | 0 | 0 | 1 | 1 | d | f | DECF f,d | Z | dest ← f−1 | |||||||
| 0 | 0 | 0 | 1 | 0 | 0 | d | f | IORWF f,d | Z | dest ← f | W, logical inclusive or | |||||||
| 0 | 0 | 0 | 1 | 0 | 1 | d | f | ANDWF f,d | Z | dest ← f & W, logical and | |||||||
| 0 | 0 | 0 | 1 | 1 | 0 | d | f | XORWF f,d | Z | dest ← f ^ W, logical exclusive or | |||||||
| 0 | 0 | 0 | 1 | 1 | 1 | d | f | ADDWF f,d | C | Z | dest ← f+W | ||||||
| 0 | 0 | 1 | 0 | 0 | 0 | d | f | MOVF f,d | Z | dest ← f | |||||||
| 0 | 0 | 1 | 0 | 0 | 1 | d | f | COMF f,d | Z | dest ← ~f, bitwise complement | |||||||
| 0 | 0 | 1 | 0 | 1 | 0 | d | f | INCF f,d | Z | dest ← f+1 | |||||||
| 0 | 0 | 1 | 0 | 1 | 1 | d | f | DECFSZ f,d | dest ← f−1, then skip if zero | ||||||||
| 0 | 0 | 1 | 1 | 0 | 0 | d | f | RRF f,d | C | dest ← CARRY<<7 | f>>1, rotate right through carry | |||||||
| 0 | 0 | 1 | 1 | 0 | 1 | d | f | RLF f,d | C | dest ← f<<1 | CARRY, rotate left through carry | |||||||
| 0 | 0 | 1 | 1 | 1 | 0 | d | f | SWAPF f,d | dest ← f<<4 | f>>4, swap nibbles | ||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | d | f | INCFSZ f,d | dest ← f+1, then skip if zero | ||||||||
| 0 | 1 | opc | bit | register | Bit operations | ||||||||||||
| 0 | 1 | 0 | 0 | bit | f | BCF f,b | Clear bit b of f | ||||||||||
| 0 | 1 | 0 | 1 | bit | f | BSF f,b | Set bit b of f | ||||||||||
| 0 | 1 | 1 | 0 | bit | f | BTFSC f,b | Skip if bit b of f is clear | ||||||||||
| 0 | 1 | 1 | 1 | bit | f | BTFSS f,b | Skip if bit b of f is set | ||||||||||
| 1 | 0 | c | k | Control transfers | |||||||||||||
| 1 | 0 | 0 | k | CALL k | Call subroutine | ||||||||||||
| 1 | 0 | 1 | k | GOTO k | Jump to address k | ||||||||||||
| 1 | 1 | opcode | 8-bit immediate | Operations with W and 8-bit literal: W ← OP(k,W) | |||||||||||||
| 1 | 1 | 0 | 0 | x | x | k | MOVLW k | W ← k | |||||||||
| 1 | 1 | 0 | 1 | x | x | k | RETLW k | W ← k, then return from subroutine | |||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | k | IORLW k | Z | W ← k | W, bitwise logical or | ||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | k | ANDLW k | Z | W ← k & W, bitwise and | ||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | k | XORLW k | Z | W ← k ^ W, bitwise exclusive or | ||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | k | (reserved) | ||||||||||
| 1 | 1 | 1 | 1 | 0 | x | k | SUBLW k | C | Z | W ← k−W (dest ← k+~W+1) | |||||||
| 1 | 1 | 1 | 1 | 1 | x | k | ADDLW k | C | Z | W ← k+W | |||||||
| 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | Description |
Enhanced mid-range core devices (14 bit)
Enhanced mid-range core devices introduce a deeper hardware stack, additional reset methods, 14 additional instructions and ‘C’ programming language optimizations. In particular. there are two INDF registers (INDF0 and INDF1), and two corresponding FSR register pairs (FSRnL and FSRnH). Special instructions use FSRn registers like address registers, with a variety of addressing modes.
| 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | Description |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | opcode | Miscellaneous instructions | |||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | RESET | Software reset | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | CALLW | Push PC, then jump to PCLATH:W | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | BRW | PC ← PC + W, relative jump using W | ||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | n | 0 | 0 | MOVIW ++FSRn | Z | Increment FSRn, then W ← INDFn | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | n | 0 | 1 | MOVIW −−FSRn | Z | Decrement FSRn, then W ← INDFn | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | n | 1 | 0 | MOVIW FSRn++ | Z | W ← INDFn, then increment FSRn | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | n | 1 | 1 | MOVIW FSRn−− | Z | W ← INDFn, then decrement FSRn | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | n | m | MOVWI using FSRn | INDFn ← W, same modes as MOVIW | |||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | k | MOVLB k | BSR ← k, move literal to bank select register | ||||||
| 1 | 1 | opcode | d | register | ALU operations: dest ← OP(f,W) | ||||||||||||
| 1 | 1 | 0 | 1 | 0 | 1 | d | f | LSLF f,d | C | Z | dest ← f << 1, logical shift left | ||||||
| 1 | 1 | 0 | 1 | 1 | 0 | d | f | LSRF f,d | C | Z | dest ← f >> 1, logical shift right | ||||||
| 1 | 1 | 0 | 1 | 1 | 1 | d | f | ASRF f,d | C | Z | dest ← f >> 1, arithmetic shift right | ||||||
| 1 | 1 | 1 | 0 | 1 | 1 | d | f | SUBWFB f,d | C | Z | dest ← f + ~W + C, subtract with carry | ||||||
| 1 | 1 | 1 | 1 | 0 | 1 | d | f | ADDWFC f,d | C | Z | dest ← f + W + C, add with carry | ||||||
| 1 | 1 | opcode | k | Operations with literal k | |||||||||||||
| 1 | 1 | 0 | 0 | 0 | 1 | 0 | n | k | ADDFSR FSRn,k | FSRn ← FSRn + k, add 6-bit signed offset | |||||||
| 1 | 1 | 0 | 0 | 0 | 1 | 1 | k | MOVLP k | PCLATH ← k, move 7-bit literal to PC latch high | ||||||||
| 1 | 1 | 0 | 0 | 1 | k | BRA k | PC ← PC + k, branch relative using 9-bit signed offset | ||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | n | k | MOVIW k[FSRn] | Z | W ← [FSRn+k], 6-bit signed offset | ||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | n | k | MOVWI k[FSRn] | [FSRn+k] ← W, 6-bit signed offset | |||||||
| 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | Description |
PIC18 high end core devices (16 bit)
In 2000, Microchip introduced the PIC18 architecture. Unlike the 17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language.[4]
The PIC18 has a 12-bit RAM address space, divided into 16 pages of 256 bytes. The 8-bit f field determines the address in combination with the a bit and the 4-bit bank select register (BSR). If a=0, the BSR is ignored and the f field is sign-extended to the range 0x000–0x07F (global RAM) or 0xF80–0xFFF (special function registers). If a=1, the f field is extended with the BSR to generate the 12-bit address.
The PIC18 extends the FSR/INDF mechanism used in previous PICmicro processors for indirect addressing in two ways. First, it provides three file select registers. The FSRn registers are 12 bits long (each split into two 8-bit portions FSR0L through FSR2H), and access to the corresponding INDFn register (INDF0 through INDF2) acts as an alias for the addressed byte.
Second, there are addressing modes. For each of the three, there is not just one INDFn register, but five, and the one used determines the addressing mode:
-
INDFn: Access the byte at locationFSRn -
POSTDECn: Access the byte atFSRn, then decrementFSRn -
POSTINCn: Access the byte atFSRn, then incrementFSRn -
PREINCn: IncrementFSRn, then access the byte at the incrementedFSRn -
PLUSWn: Access the byte atFSRn + W(indexed addressing)
There are also instructions to directly load an FSR pair with a 12-bit address, and a MOVFF instruction that moves a byte between two 12-bit addresses.
| 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | N ? | Description | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | opcode | Miscellaneous instructions | ||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | NOP | No operation | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | SLEEP | Go into standby mode | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | CLRWDT | Restart watchdog timer | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | PUSH | Push PC on top of stack | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | POP | Pop (and discard) top of stack | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | DAW | C | Decimal adjust W | |||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | TBLRD∗ | Table read: TABLAT ← mem[TBLPTR] | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | TBLRD∗+ | Table read with postincrement | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | TBLRD∗− | Table read with postdecrement | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | TBLRD+∗ | Table read with pre-increment | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | mod | TBLWR | Table write, same modes as TBLRD | |||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | s | RETFIE [, FAST] | Return from interrupt | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | s | RETURN [, FAST] | Return from subroutine | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | CALLW* | Push PC, jump to PCLATU:PCLATH:W | ||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | RESET | 0 | 0 | 0 | Software reset | |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | —0— | k | MOVLB | Move literal k to bank select register | ||||||||||
| 0 | 0 | 0 | 0 | 1 | opcode | literal | Literal operations: W ← OP(k,W) | ||||||||||||||
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | k | SUBLW k | W ← k − W | |||||||||||
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | k | IORLW k | W ← k | W, logical inclusive or | |||||||||||
| 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | k | XORLW k | W ← k ^ W, exclusive or | |||||||||||
| 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | k | ANDLW k | W ← k & W, logical and | |||||||||||
| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | k | RETLW k | RETURN W ← k | |||||||||||
| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | k | MULLW k | W ← k × W | |||||||||||
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | k | MOVLW k | W ← k | |||||||||||
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | k | ADDLW k | W ← k + W | |||||||||||
| 0 | opcode | d | a | register | ALU operations: dest ← OP(f,W) | ||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | a | f | MULWF f,a | PRODH:PRODL ← W × f (unsigned) | |||||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | d | a | f | DECF f,d,a | C | Z | N | dest ← f − 1 | ||||||||
| 0 | 0 | 0 | 1 | 0 | 0 | d | a | f | IORWF f,d,a | Z | N | dest ← f | W, logical inclusive or | |||||||||
| 0 | 0 | 0 | 1 | 0 | 1 | d | a | f | ANDWF f,d,a | Z | N | dest ← f & W, logical and | |||||||||
| 0 | 0 | 0 | 1 | 1 | 0 | d | a | f | XORWF f,d,a | Z | N | dest ← f ^ W, exclusive or | |||||||||
| 0 | 0 | 0 | 1 | 1 | 1 | d | a | f | COMF f,d,a | Z | N | dest ← ~f, bitwise complement | |||||||||
| 0 | 0 | 1 | 0 | 0 | 0 | d | a | f | ADDWFC f,d,a | C | Z | N | dest ← f + W + C | ||||||||
| 0 | 0 | 1 | 0 | 0 | 1 | d | a | f | ADDWF f,d,a | C | Z | N | dest ← f + W | ||||||||
| 0 | 0 | 1 | 0 | 1 | 0 | d | a | f | INCF f,d,a | C | Z | N | dest ← f + 1 | ||||||||
| 0 | 0 | 1 | 0 | 1 | 1 | d | a | f | DECFSZ f,d,a | dest ← f − 1, skip if 0 | |||||||||||
| 0 | 0 | 1 | 1 | 0 | 0 | d | a | f | RRCF f,d,a | C | Z | N | dest ← f>>1 | C<<7, rotate right through carry | ||||||||
| 0 | 0 | 1 | 1 | 0 | 1 | d | a | f | RLCF f,d,a | C | Z | N | dest ← f<<1 | C, rotate left through carry | ||||||||
| 0 | 0 | 1 | 1 | 1 | 0 | d | a | f | SWAPF f,d,a | dest ← f<<4 | f>>4, swap nibbles | |||||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | d | a | f | INCFSZ f,d,a | dest ← f + 1, skip if 0 | |||||||||||
| 0 | 1 | 0 | 0 | 0 | 0 | d | a | f | RRNCF f,d,a | Z | N | dest ← f>>1 | f<<7, rotate right (no carry) | |||||||||
| 0 | 1 | 0 | 0 | 0 | 1 | d | a | f | RLNCF f,d,a | Z | N | dest ← f<<1 | f>>7, rotate left (no carry) | |||||||||
| 0 | 1 | 0 | 0 | 1 | 0 | d | a | f | INFSNZ f,d,a | dest ← f + 1, skip if not 0 | |||||||||||
| 0 | 1 | 0 | 0 | 1 | 1 | d | a | f | DCFSNZ f,d,a | dest ← f − 1, skip if not 0 | |||||||||||
| 0 | 1 | 0 | 1 | 0 | 0 | d | a | f | MOVF f,d,a | Z | N | dest ← f | |||||||||
| 0 | 1 | 0 | 1 | 0 | 1 | d | a | f | SUBFWB f,d,a | C | Z | N | dest ← W + ~f + C (dest ← W − f − C̅) | ||||||||
| 0 | 1 | 0 | 1 | 1 | 0 | d | a | f | SUBWFB f,d,a | C | Z | N | dest ← f + ~W + C (dest ← f − W − C̅) | ||||||||
| 0 | 1 | 0 | 1 | 1 | 1 | d | a | f | SUBWF f,d,a | C | Z | N | dest ← f − W (dest ← f + ~W + 1) | ||||||||
| 0 | 1 | 1 | 0 | opcode | a | register | ALU operations, do not write to W | ||||||||||||||
| 0 | 1 | 1 | 0 | 0 | 0 | 0 | a | f | CPFSLT f,a | skip if f < W (unsigned) | |||||||||||
| 0 | 1 | 1 | 0 | 0 | 0 | 1 | a | f | CPFSEQ f,a | skip if f == W | |||||||||||
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | a | f | CPFSGT f,a | skip if f > W (unsigned) | |||||||||||
| 0 | 1 | 1 | 0 | 0 | 1 | 1 | a | f | TSTFSZ f,a | skip if f == 0 | |||||||||||
| 0 | 1 | 1 | 0 | 1 | 0 | 0 | a | f | SETF f,a | f ← 0xFF | |||||||||||
| 0 | 1 | 1 | 0 | 1 | 0 | 1 | a | f | CLRF f,a | 1 | f ← 0, PSR.Z ← 1 | ||||||||||
| 0 | 1 | 1 | 0 | 1 | 1 | 0 | a | f | NEGF f,a | C | Z | N | f ← −f | ||||||||
| 0 | 1 | 1 | 0 | 1 | 1 | 1 | a | f | MOVWF f,a | f ← W | |||||||||||
| 0 | 1 | 1 | 1 | bit | a | f | BTG f,b,a | Toggle bit b of f | |||||||||||||
| 1 | 0 | opc | bit | a | register | Bit operations | |||||||||||||||
| 1 | 0 | 0 | 0 | bit | a | f | BSF f,b,a | Set bit b of f | |||||||||||||
| 1 | 0 | 0 | 1 | bit | a | f | BCF f,b,a | Clear bit b of f | |||||||||||||
| 1 | 0 | 1 | 0 | bit | a | f | BTFSS f,b,a | Skip if bit b of f is set | |||||||||||||
| 1 | 0 | 1 | 1 | bit | a | f | BTFSC f,b,a | Skip if bit b of f is clear | |||||||||||||
| 1 | 1 | 0 | opc | address | Large-address operations | ||||||||||||||||
| 1 | 1 | 0 | 0 | source | MOVFF s,d | Move absolute | |||||||||||||||
| 1 | 1 | 1 | 1 | destination | |||||||||||||||||
| 1 | 1 | 0 | 1 | 0 | n | BRA n | Branch to PC + 2n | ||||||||||||||
| 1 | 1 | 0 | 1 | 1 | n | RCALL n | Subroutine call to PC + 2n | ||||||||||||||
| 1 | 1 | 1 | 0 | 0 | cond | n | Conditional branch (to PC+2n) | ||||||||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | n | BZ n | Branch if PSR.Z is set | |||||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | n | BNZ n | Branch if PSR.Z is clear | |||||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | n | BC n | Branch if PSR.C is set | |||||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | n | BNC n | Branch if PSR.C is clear | |||||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | n | BOV n | Branch if PSR.V is set | |||||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | n | BNOV n | Branch if PSR.V is clear | |||||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | n | BN n | Branch if PSR.N is set | |||||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | n | BNN n | Branch if PSR.N is clear | |||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | opc | k | Extensions for using FSR2 as software stack pointer* | |||||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | n | k | ADDFSR n,k* | FSRn += k | ||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | k | ADDULNK k* | FSR2 += k, pop PC | |||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | n | k | SUBFSR n,k* | FSRn −= k | ||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | k | ADDULNK k* | FSR2 −= k, pop PC | |||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | k | PUSHL k* | [FSR2] ← k, decrement FSR2 | |||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | s | MOVSF src,f * | f ← FSR2[s] | ||||||||||
| 1 | 1 | 1 | 1 | f | |||||||||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | s | MOVSD src,dst* | FSR2[d] ← FSR2[s] | ||||||||||
| 1 | 1 | 1 | 1 | —0— | d | ||||||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | opc | k | 2-word instructions | |||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | s | k (lsbits) | CALL k[, FAST] | Call subroutine (20-bit address) | |||||||||||
| 1 | 1 | 1 | 1 | k (msbits) | |||||||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | f | k (msb) | LFSR f,k | Move 12-bit literal to FSRf | ||||||||
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | k (lsbits) | |||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | k (lsbits) | GOTO k | Absolute jump, PC ← k (20-bit address) | |||||||||||
| 1 | 1 | 1 | 1 | k (msbits) | |||||||||||||||||
| 1 | 1 | 1 | 1 | k | No operation, second word of 2-word instructions | ||||||||||||||||
| 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | N ? | Description | |
*: These extended instructions are only available on some models, and then only if the XINST configuration bit is set.
PIC24 and dsPIC 16-bit microcontrollers
In 2001, Microchip introduced the dsPIC series of chips,[6] which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include digital signal processing capabilities in addition.
Instructions come in two main varieties. One is like the classic one-operand PIC instructions, with an operation between W0 and a value in a specified f register (i.e. the first 8K of RAM), and a destination select bit selecting which is updated with the result. The W registers are memory-mapped, so the f operand may specify a W register.
The other form, new to the PIC24, specifies three W register operands, two of which allow a 3-bit addressing mode specification:
| source operand | destination operand | Description | ||||
|---|---|---|---|---|---|---|
| ppp | Reg | Syntax | qqq | Reg | Syntax | |
| 000 | ssss | Ws | 000 | dddd | Wd | Register direct |
| 001 | ssss | [Ws] | 001 | dddd | [Wd] | Indirect |
| 010 | ssss | [Ws−−] | 010 | dddd | [Wd−−] | Indirect with postdecrement |
| 011 | ssss | [Ws++] | 011 | dddd | [Wd++] | Indirect with postincrement |
| 100 | ssss | [−−Ws] | 100 | dddd | [−−Wd] | Indirect with predecrement |
| 101 | ssss | [++Ws] | 101 | dddd | [++Wd] | Indirect with preincrement |
| 11k | kkkk | #u5 | (Unused, illegal) | 5-bit unsigned immediate | ||
| 11x | ssss | [Ws+Ww] | 11x | dddd | [Wd+Ww] | Indirect with register offset |
The register offset addressing mode is only available for the MOV src,dst instruction, where the Ww register may be used as a register offset for the source, destination, or both. All other instructions use this encoding for an unsigned 5-bit immediate source instead.
For the operands to TBLRD and TBLWT which access program memory, only the indirect modes are allowed, and refer to addresses in code memory.
A few instructions are 2 words long. The second word is a NOP, which includes up to 16 bits of additional immediate operand.
| 2 3 | 2 2 | 2 1 | 2 0 | 1 9 | 1 8 | 1 7 | 1 6 | 1 5 | 1 4 | 1 3 | 1 2 | 1 1 | 1 0 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | Mnemonic | C ? | Z ? | N ? | Description |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | opcode | offset | Control transfers | ||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | — | NOP | No operation | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | —0— | n<22:16> | CALL/GOTO addr23 | (second word) | |||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | n | DO #k,addr | (second word) | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | opc | —0— | a | Computed control transfer (to 16-bit Wa) | ||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | —0— | a | CALL Ra | Push PC, jump to Wa | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | —0— | a | RCALL Ra | Push PC, jump to PC+2×Wa | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | —0— | a | GOTO Ra | Jump to Wa | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | —0— | a | BRA Ra | Jump to PC+2×Wa | ||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | n<15:1> | 0 | CALL addr23 | Push PC, jump to absolute address | |||||||||||||||||
| —0— | —0— | n<22:16> | ||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | — | (Reserved) | |||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | n | 0 | GOTO addr23 | Jump to absolute address | |||||||||||||||||
| —0— | —0— | n<22:16> | ||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | B | k | d | RETLW[.B] #k,Wd | Wd = k, pop PC | |||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | —0— | RETURN | pop PC | ||||||||||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | —0— | RETFIE | C | Z | N | pop SR, PC | |||||||||||||
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | n | RCALL address | Push PC, PC += 2×s16 | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | k | DO #k,addr | Zero-overhead loop: k+1 is repeat count, PC+2×n last instruction | ||||||||||||||||
| —0— | n | |||||||||||||||||||||||||||
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | k | REPEAT #k | Repeat next instruction k+1 times | ||||||||||||||||
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | n | RCALL address | Push PC, PC += 2×s16 | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 1 | 0 | 1 | — | (Reserved) | ||||||||||||||||||||
| 0 | 0 | 0 | 0 | 1 | 1 | 0 | a | n | BRA Oa, addr | If accumulator a overflowed/saturated, PC += 2×simm16 | ||||||||||||||||||
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | a | n | BRA Sa, addr | |||||||||||||||||||
| 0 | opcode | w | B | q | d | p | s | Reverse subtract: dest ← source − Ww | ||||||||||||||||||||
| 0 | 0 | 0 | 1 | 0 | w | B | q | d | p | s | SUBR[.B] Ww,src,dst | C | Z | N | dst ← src − Ww = src + ~Ww + 1) | |||||||||||||
| 0 | 0 | 0 | 1 | 1 | w | B | q | d | p | s | SUBBR[.B] Ww,src,dst | C | Z | N | dst ← src − Ww − C̅ = src + ~Ww + C | |||||||||||||
| 0 | 0 | 1 | 0 | k | d | MOV #k,Wd | Wd ← #imm16 | |||||||||||||||||||||
| 0 | 0 | 1 | 1 | cond | n | Conditional branch to PC+2×n | ||||||||||||||||||||||
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | n | BRA OV,addr | ...if PSR.V is set | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | n | BRA C,addr | ...if PSR.C is set | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | n | BRA Z,addr | ...if PSR.Z is set | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | n | BRA N,addr | ...if PSR.N is set | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | n | BRA LE,addr | ...if PSR.Z, or PSR.N ≠ PSR.V | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | n | BRA LT,addr | ...if PSR.N ≠ PSR.V | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | n | BRA LEU,addr | ...if PSR.Z is set, or PSR.C is clear | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | n | BRA addr | ...unconditionally | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | n | BRA NOV,addr | ...if PSR.V is clear | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | n | BRA NC,addr | ...if PSR.C is clear | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | n | BRA NZ,addr | ...if PSR.Z is clear | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | n | BRA NN,addr | ...if PSR.N is clear | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | n | BRA GT,addr | ...if PSR.Z is clear, and PSR.N = PSR.V | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | n | BRA GE,addr | ...if PSR.N = PSR.V | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | n | BRA GTU,addr | ...if PSR.Z is clear, and PSR.C is set | ||||||||||||||||||
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | n | (Reserved) | |||||||||||||||||||
| 0 | opcode | w | B | q | d | p | s | ALU operations: dest ← OP(Ww,source) | ||||||||||||||||||||
| 0 | 1 | 0 | 0 | 0 | w | B | q | d | p | s | ADD[.B] Ww,src,dst | C | Z | N | dst ← Ww + src | |||||||||||||
| 0 | 1 | 0 | 0 | 1 | w | B | q | d | p | s | ADDC[.B] Ww,src,dst | C | Z | N | dst ← Ww + src + C | |||||||||||||
| 0 | 1 | 0 | 1 | 0 | w | B | q | d | p | s | SUB[.B] Ww,src,dst | C | Z | N | dst ← Ww − src | |||||||||||||
| 0 | 1 | 0 | 1 | 1 | w | B | q | d | p | s | SUBB[.B] Ww,src,dst | C | Z | N | dst ← Ww − ~src − C̅ = Ww + ~src + C | |||||||||||||
| 0 | 1 | 1 | 0 | 0 | w | B | q | d | p | s | AND[.B] Ww,src,dst | Z | N | dst ← Ww & src | ||||||||||||||
| 0 | 1 | 1 | 0 | 1 | w | B | q | d | p | s | XOR[.B] Ww,src,dst | Z | N | dst ← Ww ^ src | ||||||||||||||
| 0 | 1 | 1 | 1 | 0 | w | B | q | d | p | s | IOR[.B] Ww,src,dst | Z | N | dst ← Ww | src | ||||||||||||||
| 0 | 1 | 1 | 1 | 1 | w | B | q | d | p | s | MOV[.B] src,dst | Z | N | dst ← src (offset mode allowed) | ||||||||||||||
| 1 | 0 | 0 | 0 | 0 | f | d | MOV f,Wd | Wd ← f | ||||||||||||||||||||
| 1 | 0 | 0 | 0 | 1 | f | s | MOV Ws,f | f ← Ws | ||||||||||||||||||||
| 1 | 0 | 0 | 1 | 0 | k | B | k | d | k | s | MOV[.B] [Ws+s10],Wd | Load with 10-bit offset | ||||||||||||||||
| 1 | 0 | 0 | 1 | 1 | k | B | k | d | k | s | MOV[.B] Ws,[Wd+s10] | Store with 10-bit offset | ||||||||||||||||
| 1 | 0 | 1 | 0 | 0 | opcode | b | Z | B | —0— | p | s | Bit operations on source | ||||||||||||||||
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | b | 0 | B | —0— | p | s | BSET[.B] #b,src | Set bit b of src | |||||||||||||
| 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | b | 0 | B | —0— | p | s | BCLR[.B] #b,src | Clear bit b of src | |||||||||||||
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | b | 0 | B | —0— | p | s | BTG[.B] #b,src | Toggle bit b of src | |||||||||||||
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | b | 0 | 0 | —0— | p | s | BTST.C #b,src | C | Set PSR.C = bit b of src | ||||||||||||
| 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | b | 1 | 0 | —0— | p | s | BTST.Z #b,src | Z | Set PSR.Z = bit b of src | ||||||||||||
| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | b | Z | 0 | —0— | p | s | BTSTS.z #b,src | C/Z | Test bit b of src (into C or Z), then set | ||||||||||||
| 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | Z | w | 0 | —0— | p | s | BTST.z Ww,src | C/Z | Test bit Ww of src | ||||||||||||
| 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | b | 0 | 0 | —0— | p | s | BTSS #b,src | Test bit, skip if set | |||||||||||||
| 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | b | 0 | 0 | —0— | p | s | BTS #b,src | Test bit, skip if clear | |||||||||||||
| 1 | 0 | 1 | 0 | 1 | opcode | b | f | Bit operations on f | ||||||||||||||||||||
| 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | b | f | b | BSET[.B] f,#b | Set bit b of f | ||||||||||||||||
| 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | b | f | BCLR.B f,#b | Clear bit b of f | |||||||||||||||||
| 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | b | f | BTG.B f,#b | Toggle bit b of f | |||||||||||||||||
| 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | b | f | BTST.B f,#b | Z | Test bit b of f | ||||||||||||||||
| 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | b | f | BTSTS.B f,#b | Z | Test bit b of f, then set | ||||||||||||||||
| 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | Z | w | 0 | —0— | p | s | BSW.z src,Ww | Copy PSW.C or PSW.Z to bit Ww of src | |||||||||||||
| 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | b | f | BTSS f,#b | Test bit, skip if set | |||||||||||||||||
| 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | b | f | BTSC f,#b | Test bit, skip if clear | |||||||||||||||||
| 1 | 0 | 1 | 1 | 0 | 0 | opcode | B | k | d | Register-immediate operations: Wd ← OP(Wd,k) | ||||||||||||||||||
| 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | B | k | d | ADD[.B] #u10,Wd | C | Z | N | Wd ← Wd + k | ||||||||||||
| 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | B | k | d | ADC[.B] #u10,Wd | C | Z | N | Wd ← Wd + k + C | ||||||||||||
| 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | B | k | d | SUB[.B] #u10,Wd | C | Z | N | Wd ← Wd − k | ||||||||||||
| 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | B | k | d | SUBB[.B] #u10,Wd | C | Z | N | Wd ← Wd − k − C̅ | ||||||||||||
| 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | B | k | d | AND[.B] #u10,Wd | Z | N | Wd ← Wd & k | |||||||||||||
| 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | B | k | d | XOR[.B] #u10,Wd | Z | N | Wd ← Wd ^ k | |||||||||||||
| 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | B | k | d | IOR[.B] #u10,Wd | Z | N | Wd ← Wd | k | |||||||||||||
| 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | B | k | d | MOV[.B] #u10,Wd | Wd ← k | |||||||||||||||
| 1 | 0 | 1 | 1 | 0 | 1 | opcode | B | D | f | ALU operations: dest ← OP(f,W0) | ||||||||||||||||||
| 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | B | D | f | ADD[.B] f[,WREG] | C | Z | N | dest ← f + W0 | ||||||||||||
| 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | B | D | f | ADC[.B] f[,WREG] | C | Z | N | dest ← f + W0 + C | ||||||||||||
| 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | B | D | f | SUB[.B] f[,WREG] | C | Z | N | dest ← f − W0 | ||||||||||||
| 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | B | D | f | SUBB[.B] f[,WREG] | C | Z | N | dest ← f − W0 + C̅ | ||||||||||||
| 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | B | D | f | AND[.B] f[,WREG] | Z | N | dest ← f & W0 | |||||||||||||
| 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | B | D | f | XOR[.B] f[,WREG] | Z | N | dest ← f ^ W0 | |||||||||||||
| 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | B | D | f | IOR[.B] f[,WREG] | Z | N | dest ← f | W0 | |||||||||||||
| 1 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | B | 1 | f | MOV[.B] WREG,f | f ← W0 | |||||||||||||||
| 1 | 0 | 1 | 1 | 1 | 0 | 0 | opc | w | d | 0 | p | s | 16×16→32 multiplication | |||||||||||||||
| 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | w | d | 0 | p | s | MUL.UU Ww,src,Wd | Wd+1:Wd ← Ww × src (unsigned) | |||||||||||||
| 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | w | d | 0 | p | s | MUL.US Ww,src,Wd | Wd+1:Wd ← Ww × src (src signed) | |||||||||||||
| 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | w | d | 0 | p | s | MUL.SU Ww,src,Wd | Wd+1:Wd ← Ww × src (Ww signed) | |||||||||||||
| 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | w | d | 0 | p | s | MUL.SS Ww,src,Wd | Wd+1:Wd ← Ww × src (signed) | |||||||||||||
| 1 | 0 | 1 | 1 | 1 | 0 | 1 | opc | B | q | d | p | s | Program memory access (indirect modes only) | |||||||||||||||
| 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | B | q | d | p | s | TBLRDL[.B] src,dst | dst ← ROM[TBLPAG:src] (bits 15:0) | |||||||||||||
| 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | B | q | d | p | s | TBLRDH[.B] src,dst | dst ← ROM[TBLPAG:src] (bits 23:16) | |||||||||||||
| 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | B | q | d | p | s | TBLWTL[.B] src,dst | ROM[TBLPAG:dst] ← src (bits 15:0) | |||||||||||||
| 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | B | q | d | p | s | TBLWTH[.B] src,dst | ROM[TBLPAG:dst] ← src (bits 23:16) | |||||||||||||
| 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | B | 0 | f | MUL[.B] f | W3:W2 ← f × W0 (unsigned) | |||||||||||||||
| 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | B | 1 | — | (Reserved) | ||||||||||||||||
| 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | — | (Reserved) | ||||||||||||||||||
| 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | — | (Reserved) | |||||||||||||||||||
| 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | —0— | d | 0 | p | s | MOV.D src,Wd | Load register pair | ||||||||||||
| 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | q | d | —0— | s | 0 | MOV.D Ws,dst | Store register pair | ||||||||||||
| 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | — | (Reserved) | |||||||||||||||||||
| 1 | 1 | 0 | 0 | 0 | m | A | S | x | y | i | j | a | DSP MAC (dsPIC only) | |||||||||||||||
| 1 | 1 | 0 | 0 | 1 | Other DSP instructions (dsPIC only) | |||||||||||||||||||||||
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | —0— | d | p | s | FF1R src,Wd | C | Find first one from right (lsb) | ||||||||||||
| 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | —0— | d | p | s | FF1L src,Wd | C | Find first one from left (msb) | ||||||||||||
| 1 | 1 | 0 | 1 | 0 | 0 | opcode | B | q | d | p | s | Shift/rotate general operand | ||||||||||||||||
| 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | B | q | d | p | s | SL[.B] src,dst | C | Z | N | dst ← src << 1, shift left (into carry) | ||||||||||
| 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | B | q | d | p | s | LSR[.B] src,dst | C | Z | N | dst ← src >> 1, logical shift right | ||||||||||
| 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | B | q | d | p | s | ASR[.B] src,dst | C | Z | N | dst ← src >> 1, arithmetic shift right | ||||||||||
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | B | q | d | p | s | RLNC[.B] src,dst | Z | N | dst ← src <<< 1, rotate left (no carry) | |||||||||||
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | B | q | d | p | s | RLC[.B] src,dst | C | Z | N | C:dst ← src:C << 1, rotate left through carry | ||||||||||
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | B | q | d | p | s | RRNC[.B] src,dst | Z | N | dst ← src >>> 1, rotate right (no carry) | |||||||||||
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | B | q | d | p | s | RRC[.B] src,dst | C | Z | N | dst:C ← C:src >> 1, rotate right through carry | ||||||||||
| 1 | 1 | 0 | 1 | 0 | 1 | opcode | B | D | f | Shift/rotate f | ||||||||||||||||||
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | B | D | f | SL[.B] f[,WREG] | C | Z | N | dest ← f << 1, shift left (into carry) | ||||||||||||
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | B | D | f | LSR[.B] f[,WREG] | C | Z | N | dest ← f >> 1, logical shift right | ||||||||||||
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | B | D | f | ASR[.B] f[,WREG] | C | Z | N | dest ← f >> 1, arithmetic shift right | ||||||||||||
| 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | B | D | f | RLNC[.B] f[,WREG] | Z | N | dest ← f <<< 1, rotate left (no carry) | |||||||||||||
| 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | B | D | f | RLC[.B] f[,WREG] | C | Z | N | C:dest ← f:C << 1, rotate left through carry | ||||||||||||
| 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | B | D | f | RRNC[.B] f[,WREG] | Z | N | dest ← f >>> 1, rotate right (no carry) | |||||||||||||
| 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | B | D | f | RRC[.B] f[,WREG] | C | Z | N | dest:C ← C:f >> 1, rotate right through carry | ||||||||||||
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | U | t | d | D | 0 | 0 | s | Divide step (prefix with REPEAT #17) | |||||||||||||
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | —0— | d | 0 | 0 | 0 | s | DIV.S Wd,Ws | C | Z | N | W0 ← Wd/Ws, W1 ← remainder | |||||||||
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | t | d | 1 | 0 | 0 | s | DIV.SD Wd,Ws | C | Z | N | W0 ← Wt:Wd/Ws, W1 ← remainder | |||||||||
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | —0— | d | 0 | 0 | 0 | s | DIV.U Wd,Ws | C | Z | N | W0 ← Wd/Ws, W1 ← remainder | |||||||||
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | t | d | 1 | 0 | 0 | s | DIV.UD Wd,Ws | C | Z | N | W0 ← Wt:Wd/Ws, W1 ← remainder | |||||||||
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | t | —0— | 0 | 0 | 0 | s | DIVF Wt,Ws | C | Z | N | W0 ← Wt:0/Ws, W1 ← remainder | |||||||||
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | — | (Reserved) | ||||||||||||||||||
| 1 | 1 | 0 | 1 | 1 | 0 | 1 | — | (Reserved) | ||||||||||||||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | opcode | w | d | i | 0 | 0 | s | Shift/rotate multiple | |||||||||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | w | d | 0 | 0 | 0 | s | SL Ww,Ws,Wd | Z | N | Wd ← Ww << Ws | ||||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | w | d | 1 | 0 | 0 | k | SL Wv,#u4,Wd | Z | N | Wd ← Ww << k | ||||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | w | d | 0 | 0 | 0 | s | LSR Ww,Ws,Wd | Z | N | Wd ← Ww >> Ws, logical shift right | ||||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | w | d | 1 | 0 | 0 | k | LSR Wv,#u4,Wd | Z | N | Wd ← Ww >> k, logical shift right | ||||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | w | d | 0 | 0 | 0 | s | ASR Ww,Ws,Wd | Z | N | Wd ← Ww >> Ws, arithmetic shift right | ||||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | w | d | 1 | 0 | 0 | k | ASR Wv,#u4,Wd | Z | N | Wd ← Ww >> k, arithmetic shift right | ||||||||||
| 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | —0— | d | p | s | FBCL src,Wd | C | Find permissible arithmetic normalization shift | |||||||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | —0— | B | 0 | 0 | 0 | p | s | CP0[.B] src | C | Z | N | Compare with zero, src − 0 | ||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | w | B | 0 | 0 | 0 | p | s | CP[.B] Ww,src | C | Z | N | Compare, Ww − src (Ww + ~src + 1) | ||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | w | B | 0 | 0 | 0 | p | s | CPB[.B] Ww,src | C | Z | N | Compare with borrow, Ww − src − C̅ (Ww + ~src + C) | ||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | B | 0 | f | CP0[.B] f | C | Z | N | Compare with zero, f − 0 | ||||||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | B | 0 | f | CP[.B] f | C | Z | N | Compare, f − W0 | ||||||||||||
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | B | 0 | f | CPB[.B] f | C | Z | N | Compare with borrow, f − W0 − C̅ (f + ~W0 + C) | ||||||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | — | (Reserved) | ||||||||||||||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | opc | w | B | —0— | s | Compare and skip | ||||||||||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | w | B | —0— | s | CPSGT[.B] Ww,Ws | ...if Ww > Ws, signed | ||||||||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | w | B | —0— | s | CPSLT[.B] Ww,Ws | ...if Ww < Ws, signed | ||||||||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | w | B | —0— | s | CPSNE[.B] Ww,Ws | ...if Ww ≠ Ws | ||||||||||||||
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | w | B | —0— | s | CPSNE[.B] Ww,Ws | ...if Ww = Ws | ||||||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | B | q | d | p | s | INC[.B] src,dst | C | Z | N | dst ← src+1 | ||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | B | q | d | p | s | INC2[.B] src,dst | C | Z | N | dst ← src+2 | ||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | B | q | d | p | s | DEC[.B] src,dst | C | Z | N | dst ← src−1 | ||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | B | q | d | p | s | DEC2[.B] src,dst | C | Z | N | dst ← src−2 | ||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | B | q | d | p | s | NEG[.B] src,dst | C | Z | N | dst ← ~src+1 | ||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | B | q | d | p | s | COM[.B] src,dst | Z | N | dst ← ~src | |||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | B | q | d | —0— | CLR[.B] dst | dst ← 0 | ||||||||||||||
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | B | q | d | —0— | SETM[.B] dst | dst ← ~0 | ||||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | B | D | f | INC[.B] f[,WREG] | C | Z | N | dest ← f+1 | ||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | B | D | f | INC2[.B] f[,WREG] | C | Z | N | dest ← f+2 | ||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | B | D | f | DEC[.B] f[,WREG] | C | Z | N | dest ← f−1 | ||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | B | D | f | DEC[.B] f[,WREG] | C | Z | N | dest ← f−2 | ||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | B | D | f | NEG[.B] f[,WREG] | C | Z | N | dest ← ~f+1 | ||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | B | D | f | COM[.B] f[,WREG] | Z | N | dest ← ~f | |||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | B | D | f | CLR[.B] f[,WREG] | dest ← 0 | |||||||||||||||
| 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | B | D | f | SETM[.B] f[,WREG] | dest ← ~0 | |||||||||||||||
| 1 | 1 | 1 | 1 | 0 | 0 | m | A | 1 | x | y | i | j | opc | DSP MPY/MAC/ED/EDAC (dsPIC only) | ||||||||||||||
| 1 | 1 | 1 | 1 | 0 | 1 | — | (Reserved) | |||||||||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | f | 0 | PUSH f | Push f on top of stack | |||||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | f | 0 | POP f | Pop f from top of stack | |||||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | k | LNK #u14 | Push W14, W14 ← W15, W15 += k | ||||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | —0— | ULNK | W15 ← W14, pop W14 | ||||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 000 | d | p | s | SE src,dst | C | Z | N | dst ← sign_extend(src), copy bit 7 to bits 15:8 | ||||||||||
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 000 | d | p | s | ZE src,dst | 1 | Z | 0 | dst ← zero_extend(src), clear bits 15:8 | ||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | k | DISI #u14 | Disable interrupt for k+1 cycles | ||||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 000 | d | 000 | s | EXCH Ws,Wd | Swap contents of registers Ws, Wd | |||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 000 | 0000 | 000 | s | DAW.B Ws | C | Decimal adjust based on C, DC | ||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | B | 000 | 0000 | 000 | s | SWAP[.B] Ws | Swap halves of Ws | |||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | —0— | RESET | Software reset | ||||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | —0— | k | PWRSAV #u1 | Go into sleep or idle mode | ||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | —0— | CLRWDT | Clear watchdog timer | |||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | —0— | POP.S | Pop shadow registers (W0–3, part of PSR) | |||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | —0— | PUSH.S | Push shadow registers (W0–3, part of PSR) | |||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | — | (Reserved) | |||||||||||||||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | — | NOPR | No operation (version #2) | ||||||||||||||||||
References
- ↑ PIC10F200/202/204/206 Data Sheet (PDF). Microchip Technology. 2007. p. 52.
- ↑ http://www.emc.com.tw/eng/products.asp
- ↑ ELAN Microelectronics Corp. (September 2005), EM78P157N 8-bit microcontroller with OTP ROM Product Specification (PDF), retrieved 2012-04-02
- ↑ http://www.microchipc.com/sourcecode/
- ↑ Microchip Technology, Inc. (2007), PIC18F1220/1320 Data Sheet (PDF), retrieved 2012-04-02
- ↑
- ↑ dsPIC30F Programmer's Reference Manual (PDF), Microchip Technology, 2008, DS70157C, retrieved 2012-07-02