POWER9

POWER9
Produced 2017
Designed by IBM
Common manufacturer(s)
Max. CPU clock rate 4 GHz[1]
Min. feature size 14 nm
Instruction set Power Architecture (Power ISA v.3.0)
Cores 12 or 24[2][3]
L1 cache 32+32 KB per core[1]
L2 cache 512 KB per core[1]
L3 cache 120 MB per chip[1]
L4 cache via Centaur[1]
Predecessor POWER8

POWER9 are a family of superscalar symmetric multiprocessors based on the Power Architecture, and introduced in August 2016, at the Hot Chips conference.[2] The POWER9 based processors will be manufactured using a 14 nm FinFET process,[3] and will come in at least four versions; 12- and 24-core versions for scale out and 12- and 24-core versions for scale up applications,[3] and possibly more since the POWER9 architecture is open for licensing and modification by the OpenPOWER Foundation members.[4]

Systems using POWER9 are slated to be available in 2017.[2]

Variants

POWER9 devices will be targeting two different markets, the scale-out and scale-up markets, each variant come in 12- and 24-core versions:[1]

Design

The POWER9 core comes in two variants, one is four-way multithreading called SMT4 and one eight-way called SMT8.[1] The SMT4- and SMT8-cores are quite similar, in that they consist of a number of so called slices fed by common schedulers. A slice is a rudimentary 64-bit single threaded processing core with load store unit (LSU), integer unit (ALU) and a vector scalar unit (VSU, doing SIMD and floating point). A super-slice is the combination of two slices. An SMT4-core consists of a 32 KB L1 cache, a 32 KB L1 data cache, an instruction fetch unit (IFU) and a instruction sequencing unit (ISU) which feeds two super-slices. An SMT8-core has two sets of L1 caches and, IFUs and ISUs to feed four super-slices. The result is that the 12-core and 24-core versions of POWER9 each consist of the same amount of slices, i.e. 96 each and the same amount of L1 cache.

A POWER9 core, whether SMT4 and SMT8, has a 12-stage pipeline (five stage shorter than its predecessor, the POWER8) but aims to retain the clock frequency of around 4 GHz.[1] It will be the first to incorporate elements of the Power ISA v.3.0 that was released in December 2015, including the VSX-3 instructions[6] The POWER9 design is made to be modular and used in more processor variants and used for licensing, on a different fabrication process than IBM's.[5] On chip are co-processors for compression and cryptography, as well as a large low-latency eDRAM L3 cache.[3]

I/O

A lot of facilities are on-chip for helping with massive off-chip I/O performance:

Supercomputers

The United States Department of Energy together with Oak Ridge National Laboratory and Lawrence Livermore National Laboratory have contracted IBM and Nvidia to build two supercomputers, the Summit and the Sierra, that will be based on POWER9 processors coupled with Nvidia's Volta GPUs. These systems are slated to go online in 2017.[8][9][10]

See also

References

  1. 1 2 3 4 5 6 7 8 9 10 11 Big Blue Aims For The Sky With Power9
  2. 1 2 3 IBM's blazing Power9 chip is coming, and here's what you need to know
  3. 1 2 3 4 5 6 OpenPOWER and the Roadmap Ahead
  4. ↑ Power9: Google gives Intel a chip-flip migraine, IBM tries to lures big biz
  5. 1 2 3 The Prospects For A Power9 Revolution
  6. ↑ Add full Power ISA 3.0 / POWER9 binutils support
  7. ↑ Nvidia's NVLink 2.0 will first appear in Power9 servers next year
  8. ↑ NVIDIA Volta, IBM POWER9 Land Contracts For New US Government Supercomputers
  9. ↑ ORNL Summit home page
  10. ↑ Lawrence Livermore signs contract with IBM
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