Princeton Application Repository for Shared-Memory Computers

PARSEC Benchmark Suite
Original author(s) Princeton University and Intel
Developer(s) Christian Bienia
Stable release
2.1 / August 13, 2009
Development status Active
Written in C/C++
Operating system Linux, OpenSolaris
Type Benchmark
License open-source
Website http://parsec.cs.princeton.edu/

The Princeton Application Repository for Shared-Memory Computers (PARSEC) is a benchmark suite composed of multithreaded emerging workloads that is used to evaluate and develop next-generation chip-multiprocessors. It was collaboratively created by Intel and Princeton University to drive research efforts on future computer systems.[1][2] Since its inception the benchmark suite has become a community project that is continued to be improved by a broad range of research institutions.[3] PARSEC is freely available and is used for both academic and non-academic research.[4][5][6]

Motivation

With the emergence of chip-multiprocessors computer manufacturers were faced with a problem: The new technology caused a disruptive change.[2][7] For the first time in computer history software would have to be rewritten in order to take advantage of the parallel nature of those processors, which means that existing programs could not be used effectively to test and develop those new types of computer systems. At that time parallel software only existed in very specialized areas. However, before chip-multiprocessors became commonly available software developers were not willing to rewrite any mainstream programs, which means hardware manufacturers did not have access to any programs for test and development purposes that represented the expected real-world program behavior accurately. This posed a hen-and-egg problem that motivated a new type of benchmark suite with parallel programs that could take full advantage of chip-multiprocessors.

PARSEC was created to break this circular dependency. It was designed to fulfill the following five objectives:[8]

  1. Focuses on multithreaded applications
  2. Includes emerging workloads
  3. Has a diverse selection of programs
  4. Workloads employ state-of-art techniques
  5. The suite supports research

Traditional benchmarks that were publicly available before PARSEC were generally limited in their scope of included application domains or typically only available in an unparallelized, serial version. Parallel programs were only prevalent in the domain of High-Performance Computing and on a much smaller scale in business environments.[9] Chip-multiprocessors however were expected to be heavily used in all areas of computing such as with parallelized consumer applications.

Workloads

The PARSEC Benchmark Suite is available in version 2.1, which includes the following workloads:[10]

References


  1. ↑ "Intel Teams with Universities on Multicore Software Suite". EDN. Retrieved 2006-08-22.
  2. 1 2 "Designing future computers with future workloads". Research@Intel. Retrieved 2008-02-26.
  3. ↑ "Intel CTO looks into the future: Measuring the value and need for multi-core". Gabe on EDA. Retrieved 2006-08-31.
  4. ↑ "The PARSEC Benchmark Suite". Princeton University. Retrieved 2008-01-05.
  5. ↑ Bhadauria, Major; Weaver, Vincent M.; McKee, Sally A. (October 2009), "Understanding PARSEC Performance on Contemporary CMPs", Proceedings of the 2009 IEEE International Symposium on Workload Characterization, IEEE
  6. ↑ Barrow-Williams, Nick; Fensch, Christian; Moore, Simon (October 2009), "A Communication Characterization of SPLASH-2 and PARSEC", Proceedings of the 2009 IEEE International Symposium on Workload Characterization, IEEE
  7. ↑ Rabaey, Jan M.; Burke, Daniel; Lutz, Ken; Wawrzynek, John (July–August 2008), "Workloads of the Future" (PDF), IEEE Design & Test of Computers, IEEE
  8. ↑ Bienia, Christian; Kumar, Sanjeev; Singh, Jaswinder Pal; Li, Kai (October 2008), "The PARSEC Benchmark Suite: Characterization and Architectural Implications", Proceedings of the 17th international conference on Parallel architectures and compilation techniques, Association for Computing Machinery, New York, NY, USA
  9. ↑ Bienia, C.; Kumar, S.; Kai Li (2008). "PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors". 2008 IEEE International Symposium on Workload Characterization. p. 47. doi:10.1109/IISWC.2008.4636090. ISBN 978-1-4244-2777-2.
  10. ↑ Bienia, Christian; Li, Kai (June 2009), "PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors", Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation, Association for Computing Machinery, New York, NY, USA
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